The present invention relates generally to the manufacture of integrated circuit devices and, more particularly, to a test structure for detecting electromigration voids and determining electromigration failure time and via bottom liner quality in dual Damascene copper interconnects.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual Damascene wiring structures. The wiring structure typically includes copper (Cu), since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum (Al)-based interconnects.
Electromigration is a term referring to the phenomenon of mass transport of metallic atoms (e.g., copper or aluminum) which make up the interconnect material, as a result of electrical current conduction therethrough. More specifically, the electron current collides with the metal ions, thereby pushing them in the direction of electron current travel. Over an extended period of time, the vacated atoms tend to cause void formations typically at one end of a line (i.e. cathode), whereas the accumulation of atoms at the other end (i.e. anode) of the line tends to cause hillock formations. Such deformation degrades line resistance and, in some instances, leads to open circuits, short circuits and device failure. This phenomenon becomes increasingly more significant in integrated circuit design, as relative current densities through metallization lines continue to increase as the linewidth dimensions shrink due to scaling.
In dual Damascene Cu interconnects, electromigration-induced voids can form in either the via portion or the line portion of the dual Damascene structure. However, the root cause(s) of the electromigration voiding may differ, depending upon the specific location of the void. For example, a void located near the bottom of a via usually indicates defects in the via, or perhaps poor coverage of the liner material. On the other hand, voiding in the line may suggest a problem at the interface between the capping layer and the metallization. As a result, it is desirable to pinpoint the failure location, e.g. in order to identify the root cause of electromigration-associated failures, and to modify the fabrication processes for reliability improvement.
In several interconnect structures of the prior art, good liner (i.e. blocking barrier) coverage has been a challenge. This is particularly true in vias with a dual Damascene interconnect structure. Problems associated with poor liner coverage include: (i) early device failure for via depletion electromigration; (ii) early device failure of stress migration with plate above type structures; and (iii) degradation of the Blech effect. This effect, also known as stress-induced backflow effect, was coined after I. Blech, who first reported this phenomenon for aluminum metal lines. The Blech effect can be summarized as follows: as the metal ions move toward the anode end of the metal line, stress build-up occurs opposing the electron flow and slowing down the metal diffusion, thus constraining void growth which can lead to device failure.
Hence in dual Damascene Cu interconnects, the via has often been the weakest link for electromigration, especially for the via depletion mode, i.e., for electrons flowing from a dual Damascene via upwards into a line. The common electromigration failure for this mode is void formation within the via. With technology scaling to 10 nm and beyond, a void in the via needed to cause an electromigration failure becomes smaller, and consequently, the failure time becomes shorter. Such scaling will also lead to an undesirable increase in via resistance. To reduce any resistance increase resulting from scaling, the Cu blocking barrier, i.e. liner, can be made thinner. However, thinning of the liner can decrease the liner's ability to block diffusion of Cu atoms between different metal levels and, consequently, weakening the Blech effect and degrading the electromigration performance. Hence it is desirable to evaluate the integrity of Cu blocking barriers.
The prior art electromigration test structures do not allow evaluation of the block barrier effect at via bottom. For example, several known electromigration test structures have a feeding line that is too large to be sufficiently sensitive for via bottom liner leakage detection and/or does not produce the requisite pushing/driving force for the Cu diffusion as needed in blocking barrier strength testing. Other electromigration test structures in the prior art suffer from the drawback that they cannot detect if electromigration-induced voids form in the feeding line or stress line/via.
There accordingly remains a need for an electromigration test structure for locating electromigration voids, determining electromigration failure time and/or assessing the quality, i.e. strength, of a via bottom liner for blocking Cu diffusion.